In recent years, III-nitride (Gallium nitride (GaN) or Aluminum Gallium nitride (AlGaN), etc.) based high-mobility transistors (HEMT) and Schottky diodes have drawn a lot of attention because of their high potential to replace Si or SiC devices for High Voltage (HV) devices applications. Both the HEMT and the diode suffer from the problem that the on-state resistance (Ron) under dynamic (e.g., switching, pulsed, RF) conditions is significantly higher than under DC conditions.
D a Sec
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
In one embodiment, a heterojunction semiconductor device is disclosed. The heterojunction semiconductor device includes a substrate and a multilayer structure disposed on the substrate. The multilayer structure includes a first layer comprising a first semiconductor disposed on top of the substrate, a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (2DEG) forms adjacent to the interface, a first terminal electrically coupled to a first area of the interface between the first layer and second layer, a second terminal electrically coupled to a second area of the interface between the first layer and second layer, and an electrically conducting channel, wherein the electrically conducting channel connects the second terminal and a region of the first layer such that electric charge can flow between the second terminal and the first layer (e.g., so that electric charge can flow into the second terminal from the first layer).
The electrically conducting channel includes an implanted region at bottom and sidewalls, wherein the electrically conducting channel is filled with a metal and the electrically conducting channel connects the second terminal and a region of the first layer such that electric charge can flow between the second terminal and the first layer. The implanted region may be thermally annealed prior to filling the electrically conducting channel with the metal. The ion implantation can be performed using elements such as Mg, Cr, Zn, etc. for p-type and Si, Be, He, etc, for n-type Gallium nitride (GaN) layer. For example, the higher-defect-density region of the first layer may comprise a region underneath the second terminal and have a higher defect density than the rest of the first layer. The higher-defect-density region of the first layer may comprise a region underneath the second terminal and have a higher defect density than a region of the first layer underneath the first terminal. The higher-defect-density region of the first layer may comprise a region underneath the second terminal and have a higher defect density than a region between the first and second terminals. Defects introduce traps (i.e. states in the bandgap of the material) via which charge carriers can propagate (so-called hopping) under influence of a strong electric field.
The electrically conducting channel may have a higher conductivity than the first layer. The electrically conducting channel may have the same conductivity as, or a different conductivity than, the second terminal.
The conducting channel may be located below the second terminal within the area of the second terminal. That is, when viewed from above the conducting channel would be within the footprint of the second terminal.
Throughout the present specification, the descriptors relating to relative orientation and position, such as “back”, “front”, “top”, “bottom” and “side” as well as any adjective and adverb derivatives thereof, are used in the sense of the orientation of the semiconductor device as presented in the drawings. However, such descriptors are not intended to be in any way limiting to an intended use of the described or claimed invention.
The conducting channel may be located below the second terminal and extend partially towards the first terminal. The electrically conducting channel may comprise a region of the first layer comprising defects. The defects may have been induced by implantation of one or more non-doping elements. In this context, a non-dopant element is an element which does not result in p-type or n-type regions when introduced into the semiconductor lattice. The non-dopant elements may comprise one or more of argon and nitrogen. The implantation doses may be in the range of 1e11 to 1e12 per cm2. An argon dose of around 1e13 per cm2 may be used.
The implantation dose may be element dependent. For example, a heavier element may require a lower dose to damage the crystal structure. The implanted area may extend, for example, from the second terminal towards the first terminal or in a patterned fashion (e.g. in stripes or dots). When implantation is used within the footprint of the second terminal (e.g. so that the implanted area is not between the second terminal and the first terminal) the dose of the implantation can be higher, up to the dose where it effectively removes the Two-Dimensional Electron Gas (2DEG).
The heterojunction semiconductor device may comprise a passivation layer comprising a semiconductor passivation layer disposed on top of the second layer. The passivation layer may comprise silicon nitride. The passivation layer may further comprise a dielectric layer disposed between the semiconductor passivation layer and the second layer. The passivation layer may comprise a semiconductor passivation layer in direct contact with the second layer.
The first semiconductor may be a first III-V semiconductor, and the second semiconductor may be a second III-V semiconductor.
The III-V semiconductors may comprise any metallic elements selected from group III of the periodic table together with any of the non-metallic elements selected from group V of the periodic table.
The III-V semiconductors may comprise one or more of the metallic elements aluminium, gallium and indium. The III-V semiconductors may comprise nitride semiconductors, or phosphide semiconductors, or arsenide semiconductors.
The III-V semiconductors may comprise any of the semiconductors Gallium Nitride, Aluminium Nitride, Indium Nitride, Aluminium Gallium Nitride, Aluminium Indium Nitride, Gallium Indium Nitride, Aluminium Gallium Indium Nitride, Gallium Phosphide, Aluminium Phosphide, Indium Phosphide, Aluminium Gallium Phosphide, Aluminium Indium Phosphide, Gallium Indium Phosphide, Aluminium Gallium Indium Phosphide, Gallium Arsenide, Aluminium Arsenide, Indium Arsenide, Aluminium Gallium Arsenide, Aluminium Indium Arsenide, Gallium Indium Arsenide, and Aluminium Gallium Indium Arsenide.
The first layer may be a p-type semiconductor doped with a first concentration of p-type dopants. The second layer may be an n-type semiconductor, or the second layer may be an undoped semiconductor, or the second layer may be a p-type semiconductor doped with a second concentration of p-type dopants where the second concentration is less than the first concentration.
The first layer may comprise Gallium Nitride. The first layer may be semi-insulating (e.g. having a resistivity typically higher than 1 M□cm). The second layer may comprise Aluminium Gallium Nitride.
The electrical coupling of the first terminal to the heterojunction device may comprise a Schottky contact with the second layer and the electrical coupling of the second terminal to the heterojunction device may comprise an Ohmic contact with the second layer, such that the device is configured to comprise a Schottky diode. In this way, each of the first and second terminals is configured to be electrically coupled to an area of the interface between the first and second layers to interact with the Two-Dimensional Electron Gas.
The heterojunction semiconductor device may comprise a third terminal electrically coupled to a third area of the heterojunction device such that the first terminal is positioned between the second terminal and the third terminal. The heterojunction semiconductor device may further comprise a third terminal electrically coupled to a third area of the heterojunction device such that the first terminal is positioned between the second terminal and the third terminal. In this way, each of the first, second and third terminals is configured to be electrically coupled to an area of the interface between the first and second layers to interact with the Two-Dimensional Electron Gas.
The third terminal may comprise a source terminal; the second terminal may comprise a drain terminal; the first terminal may comprise a gate terminal; whereby the heterojunction semiconductor device is configured to comprise a High Electron Mobility Transistor (HEMT).
The heterojunction semiconductor device may comprise a dielectric layer disposed between the second layer and the semiconductor passivation layer. The third terminal includes a source terminal electrically coupled to the second layer such that electric charge can flow from the third terminal to the second layer. The second terminal includes a drain terminal electrically coupled the second layer such that electric charge can flow from the second layer into the second terminal. The first terminal includes a gate terminal disposed on top of the dielectric layer. The heterojunction semiconductor device is configured to comprise a Metal-Insulator-Semiconductor High Electron Mobility Transistor.
There may be provided an integrated circuit comprising any heterojunction semiconductor device disclosed herein.
The metal conducting channel may be provided in practice by first etching through to the first layer to form a recess (e.g., after dry etching the contact holes through the passivation layer, typically with a fluorine dry etch chemistry). Then the ohmic metal is deposited, contacting the region wherein the 2DEG will be formed in-use (as in conventional heterojunction devices) and the first layer (e.g., comprising p-type GaN). For GaN/AlGaN embodiments, the recess may be formed using a BCl3/Cl2-based dry etch chemistry.
Note that figures are not drawn to scale. Intermediate steps between figure transitions have been omitted so as not to obfuscate the disclosure. Those intermediate steps are known to a person skilled in the art.